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Searched refs:vhdl_port_decl (Results 1 – 3 of 3) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dscope.cc598 (new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_IN)); in declare_one_signal()
602 vhdl_port_decl *decl = in declare_one_signal()
603 new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_OUT); in declare_one_signal()
631 (new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_INOUT)); in declare_one_signal()
H A Dvhdl_syntax.cc126 void vhdl_entity::add_port(vhdl_port_decl *decl) in add_port()
451 void vhdl_port_decl::emit(std::ostream &of, int level) const in emit()
474 void vhdl_port_decl::ensure_readable() in ensure_readable()
484 bool vhdl_port_decl::is_readable() const in is_readable()
H A Dvhdl_syntax.hh722 class vhdl_port_decl : public vhdl_decl { class
724 vhdl_port_decl(const char *name, vhdl_type *type, in vhdl_port_decl() function in vhdl_port_decl
907 void add_port(vhdl_port_decl *decl);