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Searched refs:vhdl_units (Results 1 – 7 of 7) sorted by relevance

/dports/cad/electric/electric-7.00/src/vhdl/
H A Dvhdlsemantic.c45 DBUNITS *vhdl_units = 0; variable
112 if (vhdl_units == 0) return; in vhdl_freesemantic()
113 while (vhdl_units->interfaces != 0) in vhdl_freesemantic()
115 intf = vhdl_units->interfaces; in vhdl_freesemantic()
116 vhdl_units->interfaces = vhdl_units->interfaces->next; in vhdl_freesemantic()
125 while (vhdl_units->bodies != 0) in vhdl_freesemantic()
127 body = vhdl_units->bodies; in vhdl_freesemantic()
128 vhdl_units->bodies = vhdl_units->bodies->next; in vhdl_freesemantic()
182 efree((CHAR *)vhdl_units); in vhdl_freesemantic()
183 vhdl_units = 0; in vhdl_freesemantic()
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H A Dvhdlsilos.c41 extern DBUNITS *vhdl_units;
79 vhdl_top_interface = vhdl_findtopinterface(vhdl_units); in vhdl_gensilos()
86 for (interfacef = vhdl_units->interfaces; interfacef != NULL; in vhdl_gensilos()
H A Dvhdlnetlisp.c41 extern DBUNITS *vhdl_units;
80 vhdl_top_interface = vhdl_findtopinterface(vhdl_units); in vhdl_gennet()
87 for (interfacef = vhdl_units->interfaces; interfacef != NULL; in vhdl_gennet()
H A Dvhdlals.c41 extern DBUNITS *vhdl_units;
201 top_interface = vhdl_findtopinterface(vhdl_units); in vhdl_genals()
208 for (interfacef = vhdl_units->interfaces; interfacef != NULL; interfacef = interfacef->next) in vhdl_genals()
H A Dvhdlquisc.c42 extern DBUNITS *vhdl_units;
116 top_interface = vhdl_findtopinterface(vhdl_units); in vhdl_genquisc()
121 for (interfacef = vhdl_units->interfaces; interfacef != NULL; in vhdl_genquisc()
/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dvhdl_syntax.cc166 int vhdl_units = std::min(units, precision); in set_time_units() local
168 if (vhdl_units >= -3) in set_time_units()
170 else if (vhdl_units >= -6) in set_time_units()
172 else if (vhdl_units >= -9) in set_time_units()
/dports/cad/yosys/yosys-yosys-0.12/frontends/verific/
H A Dverific.cc2184 Array veri_modules, vhdl_units; in verific_import() local
2204 vhdl_units.InsertLast(vhdl_unit); in verific_import()
2207 netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params); in verific_import()
3127 Array veri_modules, vhdl_units; in execute() local
3143 vhdl_units.InsertLast(vhdl_unit); in execute()
3161 Array *netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters); in execute()