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Searched refs:vhdl_var_decl (Results 1 – 5 of 5) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dstmt.cc216 (new vhdl_var_decl(make_safe_name(sig), type)); in draw_block()
271 vhdl_var_decl* shadow_decl = in make_assign_lhs()
272 new vhdl_var_decl(shadow_name, decl->get_type()); in make_assign_lhs()
551 vhdl_decl* tmp_decl = new vhdl_var_decl(ss.str(), rhs->get_type()); in make_assignment()
1065 (new vhdl_var_decl(tmp_name, new vhdl_type(*test_type))); in draw_case_test()
H A Dlogic.cc190 proc->get_scope()->add_decl(new vhdl_var_decl("UDP_Inputs", tmp_type)); in seq_udp_logic()
H A Dvhdl_syntax.hh678 class vhdl_var_decl : public vhdl_decl { class
680 vhdl_var_decl(const string& name, const vhdl_type *type) in vhdl_var_decl() function in vhdl_var_decl
H A Dscope.cc813 (new vhdl_var_decl(signame, sigtype)); in draw_function()
836 new vhdl_var_decl(signame, sigtype)); in draw_function()
H A Dvhdl_syntax.cc489 void vhdl_var_decl::emit(std::ostream &of, int level) const in emit()