Searched refs:vmfne_vv (Results 1 – 13 of 13) sorted by relevance
/dports/emulators/qemu5/qemu-5.2.0/target/riscv/ |
H A D | insn32.decode | 520 vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm
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/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/ |
H A D | riscv.mk.in | 782 vmfne_vv \
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H A D | encoding.h | 3720 DECLARE_INSN(vmfne_vv, MATCH_VMFNE_VV, MASK_VMFNE_VV)
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/dports/emulators/qemu60/qemu-6.0.0/target/riscv/ |
H A D | insn32.decode | 520 vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/ |
H A D | insn32.decode | 576 vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm
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/dports/emulators/qemu/qemu-6.2.0/target/riscv/ |
H A D | insn32.decode | 576 vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm
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/dports/devel/openocd/openocd-0.11.0/src/target/riscv/ |
H A D | encoding.h | 2505 DECLARE_INSN(vmfne_vv, MATCH_VMFNE_VV, MASK_VMFNE_VV)
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/dports/lang/v8/v8-9.6.180.12/src/compiler/backend/riscv64/ |
H A D | code-generator-riscv64.cc | 2525 __ vmfne_vv(v0, i.InputSimd128Register(1), i.InputSimd128Register(0)); in AssembleArchInstruction() local
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/dports/lang/v8/v8-9.6.180.12/src/wasm/baseline/riscv64/ |
H A D | liftoff-assembler-riscv64.h | 1964 vmfne_vv(v0, rhs.fp().toV(), lhs.fp().toV()); in emit_f32x4_ne()
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/dports/emulators/qemu5/qemu-5.2.0/target/riscv/insn_trans/ |
H A D | trans_rvv.c.inc | 2177 GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/insn_trans/ |
H A D | trans_rvv.c.inc | 2140 GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
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/dports/emulators/qemu/qemu-6.2.0/target/riscv/insn_trans/ |
H A D | trans_rvv.c.inc | 2144 GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
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/dports/emulators/qemu60/qemu-6.0.0/target/riscv/insn_trans/ |
H A D | trans_rvv.c.inc | 2177 GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
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