| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/MC/RISCV/rvv/ |
| H A D | vsetvl.s | 17 vsetvl a2, a0, a1 label
18 # CHECK-INST: vsetvl a2, a0, a1
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/MC/RISCV/rvv/ |
| H A D | vsetvl.s | 17 vsetvl a2, a0, a1 label
18 # CHECK-INST: vsetvl a2, a0, a1
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/MC/RISCV/rvv/ |
| H A D | vsetvl.s | 77 vsetvl a2, a0, a1 label
78 # CHECK-INST: vsetvl a2, a0, a1
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/MC/RISCV/rvv/ |
| H A D | vsetvl.s | 77 vsetvl a2, a0, a1 label
78 # CHECK-INST: vsetvl a2, a0, a1
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/MC/RISCV/rvv/ |
| H A D | vsetvl.s | 77 vsetvl a2, a0, a1 label
78 # CHECK-INST: vsetvl a2, a0, a1
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/MC/RISCV/rvv/ |
| H A D | vsetvl.s | 77 vsetvl a2, a0, a1 label
78 # CHECK-INST: vsetvl a2, a0, a1
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/MC/RISCV/rvv/ |
| H A D | vsetvl.s | 77 vsetvl a2, a0, a1 label
78 # CHECK-INST: vsetvl a2, a0, a1
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/MC/RISCV/rvv/ |
| H A D | vsetvl.s | 77 vsetvl a2, a0, a1 label
78 # CHECK-INST: vsetvl a2, a0, a1
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/MC/RISCV/rvv/ |
| H A D | vsetvl.s | 77 vsetvl a2, a0, a1 label
78 # CHECK-INST: vsetvl a2, a0, a1
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/MC/RISCV/rvv/ |
| H A D | vsetvl.s | 77 vsetvl a2, a0, a1
78 # CHECK-INST: vsetvl a2, a0, a1
|
| /dports/emulators/qemu5/qemu-5.2.0/target/riscv/ |
| H A D | insn32.decode | 594 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
|
| /dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/ |
| H A D | riscv.mk.in | 885 vsetvl \
|
| /dports/emulators/qemu60/qemu-6.0.0/target/riscv/ |
| H A D | insn32.decode | 594 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
|
| /dports/lang/v8/v8-9.6.180.12/src/codegen/riscv64/ |
| H A D | assembler-riscv64.h | 685 inline void vsetvl(VSew vsew, Vlmul vlmul, TailAgnosticType tail = tu,
690 void vsetvl(Register rd, Register rs1, Register rs2);
1238 assm_->vsetvl(sew_, lmul_); in set()
|
| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/ |
| H A D | insn32.decode | 650 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
|
| /dports/emulators/qemu/qemu-6.2.0/target/riscv/ |
| H A D | insn32.decode | 650 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/clang/include/clang/Basic/ |
| H A D | riscv_vector.td | 1422 // 6.1. vsetvli/vsetvl instructions
1429 // vsetvl is a macro because for it require constant integers in SEW and LMUL.
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/clang/include/clang/Basic/ |
| H A D | riscv_vector.td | 1422 // 6.1. vsetvli/vsetvl instructions
1429 // vsetvl is a macro because for it require constant integers in SEW and LMUL.
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/clang/include/clang/Basic/ |
| H A D | riscv_vector.td | 1422 // 6.1. vsetvli/vsetvl instructions
1429 // vsetvl is a macro because for it require constant integers in SEW and LMUL.
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/clang/include/clang/Basic/ |
| H A D | riscv_vector.td | 1422 // 6.1. vsetvli/vsetvl instructions
1429 // vsetvl is a macro because for it require constant integers in SEW and LMUL.
|
| /dports/lang/clang-mesa/clang-13.0.1.src/include/clang/Basic/ |
| H A D | riscv_vector.td | 1422 // 6.1. vsetvli/vsetvl instructions
1429 // vsetvl is a macro because for it require constant integers in SEW and LMUL.
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoV.td | 371 "vsetvl", "$rd, $rs1, $rs2">;
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoV.td | 371 "vsetvl", "$rd, $rs1, $rs2">;
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/clang/include/clang/Basic/ |
| H A D | riscv_vector.td | 1530 // 6.1. vsetvli/vsetvl instructions
1538 // vsetvl is a macro because for it require constant integers in SEW and LMUL.
|
| /dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/disasm/ |
| H A D | disasm.cc | 1078 DEFINE_RTYPE(vsetvl); in disassembler_t()
|