Searched refs:vssub_vv (Results 1 – 14 of 14) sorted by relevance
/dports/lang/v8/v8-9.6.180.12/test/cctest/ |
H A D | test-disasm-riscv64.cc | 548 COMPARE(vssub_vv(v2, v3, v4), "8e320157 vssub.vv v2, v3, v4"); in TEST()
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/dports/emulators/qemu5/qemu-5.2.0/target/riscv/ |
H A D | insn32.decode | 435 vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
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/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/ |
H A D | riscv.mk.in | 637 vssub_vv \
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H A D | encoding.h | 3838 DECLARE_INSN(vssub_vv, MATCH_VSSUB_VV, MASK_VSSUB_VV)
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/dports/emulators/qemu60/qemu-6.0.0/target/riscv/ |
H A D | insn32.decode | 435 vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/ |
H A D | insn32.decode | 491 vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
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/dports/emulators/qemu/qemu-6.2.0/target/riscv/ |
H A D | insn32.decode | 491 vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
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/dports/lang/v8/v8-9.6.180.12/src/compiler/backend/riscv64/ |
H A D | code-generator-riscv64.cc | 1969 __ vssub_vv(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local 1987 __ vssub_vv(i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction() local
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/dports/devel/openocd/openocd-0.11.0/src/target/riscv/ |
H A D | encoding.h | 2622 DECLARE_INSN(vssub_vv, MATCH_VSSUB_VV, MASK_VSSUB_VV)
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/dports/lang/v8/v8-9.6.180.12/src/wasm/baseline/riscv64/ |
H A D | liftoff-assembler-riscv64.h | 2190 vssub_vv(dst.fp().toV(), lhs.fp().toV(), rhs.fp().toV()); in emit_i8x16_sub_sat_s()
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/dports/emulators/qemu5/qemu-5.2.0/target/riscv/insn_trans/ |
H A D | trans_rvv.c.inc | 1757 GEN_OPIVV_TRANS(vssub_vv, opivv_check)
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/insn_trans/ |
H A D | trans_rvv.c.inc | 1717 GEN_OPIVV_TRANS(vssub_vv, opivv_check)
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/dports/emulators/qemu/qemu-6.2.0/target/riscv/insn_trans/ |
H A D | trans_rvv.c.inc | 1721 GEN_OPIVV_TRANS(vssub_vv, opivv_check)
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/dports/emulators/qemu60/qemu-6.0.0/target/riscv/insn_trans/ |
H A D | trans_rvv.c.inc | 1757 GEN_OPIVV_TRANS(vssub_vv, opivv_check)
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