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Searched refs:warn_sens_entire_vec (Results 1 – 3 of 3) sorted by relevance

/dports/cad/iverilog/verilog-11.0/
H A Dcompiler.h101 extern bool warn_sens_entire_vec;
H A Dmain.cc166 bool warn_sens_entire_vec = false; variable
743 warn_sens_entire_vec = true; in read_iconfig_file()
H A Dnet_nex_input.cc160 if (base_ && ! always_sens && warn_sens_entire_vec) { in nex_input()