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Searched refs:whens_ (Results 1 – 2 of 2) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dvhdl_syntax.cc758 whens_.push_back(when); in add_condition()
765 if (!whens_.empty()) { in emit()
766 for (std::list<when_part_t>::const_iterator it = whens_.begin(); in emit()
767 it != whens_.end(); in emit()
1178 when_list_t::const_iterator it = whens_.begin(); in emit()
1179 while (it != whens_.end()) { in emit()
1188 if (++it != whens_.end() || others_ != NULL) { in emit()
1205 whens_.push_back(when); in add_condition()
H A Dvhdl_syntax.hh325 when_list_t whens_; member in vhdl_cassign_stmt
341 when_list_t whens_; member in vhdl_with_select_stmt