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Searched refs:wide_input_bus (Results 1 – 1 of 1) sorted by relevance

/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_sv_conditional.v73 logic [8*16-1:0] wide_input_bus; register
91 wide_input_bus = {8'hf5,
116 .wide_input_bus (wide_input_bus[8*16-1:0]),
151 (input logic [8*16-1:0] wide_input_bus, port
197 (.wide_input_bus (wide_input_bus),
203 (.wide_input_bus (wide_input_bus),
209 (.wide_input_bus (wide_input_bus),
215 (.wide_input_bus (wide_input_bus),
221 (.wide_input_bus (wide_input_bus),
227 (.wide_input_bus (wide_input_bus),
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