Searched refs:wire_bit (Results 1 – 3 of 3) sorted by relevance
| /dports/cad/yosys/yosys-yosys-0.12/passes/techmap/ |
| H A D | iopadmap.cc | 290 SigBit wire_bit(wire, i); in execute() local
296 if (tbuf_bits.count(wire_bit)) in execute()
297 tbuf_cell = tbuf_bits.at(wire_bit); in execute()
301 bool is_driven = driven_bits.count(wire_bit); in execute()
314 data_sig = wire_bit; in execute()
320 if (z_conns.count(wire_bit)) in execute()
321 remove_conns.insert(z_conns[wire_bit]); in execute()
364 module->connect(wire_bit, data_sig); in execute()
432 SigBit wire_bit(wire, i); in execute() local
437 cell->setPort(RTLIL::escape_id(portname_int), wire_bit); in execute()
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| H A D | clkbufmap.cc | 244 SigBit wire_bit(wire, i); in execute() local
245 SigBit mapped_wire_bit = sigmap(wire_bit); in execute()
252 …} else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute(ID:… in execute()
297 SigBit wire_bit(wire, i); in execute() local
298 SigBit mapped_wire_bit = sigmap(wire_bit); in execute()
317 SigBit wire_bit(wire, i); in execute() local
318 SigBit mapped_wire_bit = sigmap(wire_bit); in execute()
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| /dports/cad/yosys/yosys-yosys-0.12/passes/opt/ |
| H A D | opt_clean.cc | 528 SigBit wire_bit = SigBit(wire, i); in rmunused_module_init() local
529 SigBit mapped_wire_bit = sigmap(wire_bit); in rmunused_module_init()
531 if (wire_bit == mapped_wire_bit) in rmunused_module_init()
546 … value conflict for %s resolving to %s but with init %s.\n", log_signal(wire_bit), log_signal(mapp… in rmunused_module_init()
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