Home
last modified time | relevance | path

Searched refs:write_octeon_c0_dcacheerr (Results 1 – 25 of 71) sorted by relevance

123

/dports/multimedia/libv4l/linux-5.13-rc2/drivers/edac/
H A Docteon_edac-pc.c76 write_octeon_c0_dcacheerr(1); in co_cache_error_event()
78 write_octeon_c0_dcacheerr(0); in co_cache_error_event()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/edac/
H A Docteon_edac-pc.c76 write_octeon_c0_dcacheerr(1); in co_cache_error_event()
78 write_octeon_c0_dcacheerr(0); in co_cache_error_event()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/edac/
H A Docteon_edac-pc.c76 write_octeon_c0_dcacheerr(1); in co_cache_error_event()
78 write_octeon_c0_dcacheerr(0); in co_cache_error_event()
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/mips/cavium-octeon/
H A Dsetup.c423 write_octeon_c0_dcacheerr(0); in octeon_check_cpu_bist()
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/mips/cavium-octeon/
H A Dsetup.c423 write_octeon_c0_dcacheerr(0); in octeon_check_cpu_bist()
/dports/multimedia/libv4l/linux-5.13-rc2/arch/mips/cavium-octeon/
H A Dsetup.c423 write_octeon_c0_dcacheerr(0); in octeon_check_cpu_bist()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/mips/include/asm/
H A Dmipsregs.h1393 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/mips/include/asm/
H A Dmipsregs.h1393 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/mips/include/asm/
H A Dmipsregs.h1393 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/mips/include/asm/
H A Dmipsregs.h1393 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/sysutils/u-boot-tools/u-boot-2020.07/arch/mips/include/asm/
H A Dmipsregs.h1394 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/mips/include/asm/
H A Dmipsregs.h1393 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/include/asm/
H A Dmipsregs.h1884 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/mips/include/asm/
H A Dmipsregs.h1884 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/include/asm/
H A Dmipsregs.h1884 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/include/asm/
H A Dmipsregs.h1884 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/include/asm/
H A Dmipsregs.h1884 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/mips/include/asm/
H A Dmipsregs.h1884 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/include/asm/
H A Dmipsregs.h1884 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/mips/include/asm/
H A Dmipsregs.h1884 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/include/asm/
H A Dmipsregs.h1884 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/include/asm/
H A Dmipsregs.h1884 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/include/asm/
H A Dmipsregs.h1884 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/include/asm/
H A Dmipsregs.h1884 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/include/asm/
H A Dmipsregs.h1884 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) macro

123