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Searched refs:xgene_enet_rd_csr (Results 1 – 9 of 9) sorted by relevance

/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_xgmac.c85 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata, in xgene_enet_rd_csr() function
228 xgene_enet_rd_csr(pdata, XG_TSIF_MSS_REG0_ADDR + offset, &data); in xgene_xgmac_set_mss()
249 xgene_enet_rd_csr(pdata, XG_LINK_STATUS_ADDR, &data); in xgene_enet_link_status()
312 xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data); in xgene_xgmac_init()
319 xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, &data); in xgene_xgmac_init()
323 xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data); in xgene_xgmac_init()
419 xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG0_ADDR, &cb); in xgene_enet_xgcle_bypass()
426 xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb); in xgene_enet_xgcle_bypass()
H A Dxgene_enet_sgmac.c45 static u32 xgene_enet_rd_csr(struct xgene_enet_pdata *p, u32 offset) in xgene_enet_rd_csr() function
268 value = xgene_enet_rd_csr(p, debug_addr); in xgene_sgmac_set_speed()
357 data = xgene_enet_rd_csr(p, enet_spare_cfg_reg); in xgene_sgmac_init()
367 data = xgene_enet_rd_csr(p, rsif_config_reg); in xgene_sgmac_init()
390 data1 = xgene_enet_rd_csr(p, pause_thres_reg); in xgene_sgmac_init()
391 data2 = xgene_enet_rd_csr(p, pause_off_thres_reg); in xgene_sgmac_init()
H A Dxgene_enet_hw.c290 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata, in xgene_enet_rd_csr() function
466 xgene_enet_rd_csr(pdata, RGMII_REG_0_ADDR, &rgmii); in xgene_gmac_set_speed()
494 xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value); in xgene_gmac_set_speed()
576 xgene_enet_rd_csr(pdata, RSIF_CONFIG_REG_ADDR, &value); in xgene_gmac_init()
638 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb); in xgene_enet_cle_bypass()
644 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb); in xgene_enet_cle_bypass()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_xgmac.c85 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata, in xgene_enet_rd_csr() function
228 xgene_enet_rd_csr(pdata, XG_TSIF_MSS_REG0_ADDR + offset, &data); in xgene_xgmac_set_mss()
249 xgene_enet_rd_csr(pdata, XG_LINK_STATUS_ADDR, &data); in xgene_enet_link_status()
312 xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data); in xgene_xgmac_init()
319 xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, &data); in xgene_xgmac_init()
323 xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data); in xgene_xgmac_init()
419 xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG0_ADDR, &cb); in xgene_enet_xgcle_bypass()
426 xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb); in xgene_enet_xgcle_bypass()
H A Dxgene_enet_sgmac.c45 static u32 xgene_enet_rd_csr(struct xgene_enet_pdata *p, u32 offset) in xgene_enet_rd_csr() function
268 value = xgene_enet_rd_csr(p, debug_addr); in xgene_sgmac_set_speed()
357 data = xgene_enet_rd_csr(p, enet_spare_cfg_reg); in xgene_sgmac_init()
367 data = xgene_enet_rd_csr(p, rsif_config_reg); in xgene_sgmac_init()
390 data1 = xgene_enet_rd_csr(p, pause_thres_reg); in xgene_sgmac_init()
391 data2 = xgene_enet_rd_csr(p, pause_off_thres_reg); in xgene_sgmac_init()
H A Dxgene_enet_hw.c290 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata, in xgene_enet_rd_csr() function
466 xgene_enet_rd_csr(pdata, RGMII_REG_0_ADDR, &rgmii); in xgene_gmac_set_speed()
494 xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value); in xgene_gmac_set_speed()
576 xgene_enet_rd_csr(pdata, RSIF_CONFIG_REG_ADDR, &value); in xgene_gmac_init()
638 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb); in xgene_enet_cle_bypass()
644 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb); in xgene_enet_cle_bypass()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_xgmac.c85 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata, in xgene_enet_rd_csr() function
228 xgene_enet_rd_csr(pdata, XG_TSIF_MSS_REG0_ADDR + offset, &data); in xgene_xgmac_set_mss()
249 xgene_enet_rd_csr(pdata, XG_LINK_STATUS_ADDR, &data); in xgene_enet_link_status()
312 xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data); in xgene_xgmac_init()
319 xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, &data); in xgene_xgmac_init()
323 xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data); in xgene_xgmac_init()
419 xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG0_ADDR, &cb); in xgene_enet_xgcle_bypass()
426 xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb); in xgene_enet_xgcle_bypass()
H A Dxgene_enet_sgmac.c45 static u32 xgene_enet_rd_csr(struct xgene_enet_pdata *p, u32 offset) in xgene_enet_rd_csr() function
268 value = xgene_enet_rd_csr(p, debug_addr); in xgene_sgmac_set_speed()
357 data = xgene_enet_rd_csr(p, enet_spare_cfg_reg); in xgene_sgmac_init()
367 data = xgene_enet_rd_csr(p, rsif_config_reg); in xgene_sgmac_init()
390 data1 = xgene_enet_rd_csr(p, pause_thres_reg); in xgene_sgmac_init()
391 data2 = xgene_enet_rd_csr(p, pause_off_thres_reg); in xgene_sgmac_init()
H A Dxgene_enet_hw.c290 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata, in xgene_enet_rd_csr() function
466 xgene_enet_rd_csr(pdata, RGMII_REG_0_ADDR, &rgmii); in xgene_gmac_set_speed()
494 xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value); in xgene_gmac_set_speed()
576 xgene_enet_rd_csr(pdata, RSIF_CONFIG_REG_ADDR, &value); in xgene_gmac_init()
638 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb); in xgene_enet_cle_bypass()
644 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb); in xgene_enet_cle_bypass()