| /dports/lang/gomacro/gomacro-2.7-304-g2f4dc7c/jit/amd64/ |
| H A D | op1.go | 61 return arch.zeroReg(asm, r)
132 arch.zeroReg(asm, dst)
143 func (arch Amd64) zeroReg(asm *Asm, dst Reg) Amd64 { func
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| H A D | shift.go | 29 return arch.zeroReg(asm, dst)
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| H A D | mov.go | 34 return arch.zeroReg(asm, dst)
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| H A D | mul.go | 41 return arch.zeroReg(asm, dst)
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| /dports/lang/gomacro/gomacro-2.7-304-g2f4dc7c/jit/arm64/ |
| H A D | op1.go | 44 arch.zeroReg(asm, dst)
54 func (arch Arm64) zeroReg(asm *Asm, dst Reg) Arm64 { func
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| /dports/games/libretro-yabause/yabause-ea5b118/yabause/src/play/src/ |
| H A D | Jitter_CodeGen_AArch64_Md.cpp | 269 auto zeroReg = GetNextTempRegisterMd(); in Emit_Md_Not_VarVar() local
271 m_assembler.Eor_16b(zeroReg, zeroReg, zeroReg); in Emit_Md_Not_VarVar()
272 m_assembler.Orn_16b(dstReg, zeroReg, src1Reg); in Emit_Md_Not_VarVar()
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| H A D | Jitter_CodeGen_AArch32_Md.cpp | 181 auto zeroReg = CAArch32Assembler::q0; in Emit_Md_Not_MemMem() local
188 m_assembler.Veor(zeroReg, zeroReg, zeroReg); in Emit_Md_Not_MemMem()
189 m_assembler.Vorn(tmpReg, zeroReg, tmpReg); in Emit_Md_Not_MemMem()
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| /dports/games/libretro-play/Play--3cd0a367b5e24c061a6310c68c9fa7f6b531ebd4/deps/CodeGen/src/ |
| H A D | Jitter_CodeGen_AArch32_Md.cpp | 387 auto zeroReg = CAArch32Assembler::q2; in Emit_Md_MakeSz_VarVar() local
399 m_assembler.Vceqz_F32(zeroReg, src1Reg); in Emit_Md_MakeSz_VarVar()
410 m_assembler.Vpaddl_I8(zeroReg, signReg); in Emit_Md_MakeSz_VarVar()
411 m_assembler.Vpaddl_I16(cstReg, zeroReg); in Emit_Md_MakeSz_VarVar()
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| H A D | Jitter_CodeGen_AArch64_Md.cpp | 207 auto zeroReg = GetNextTempRegisterMd(); in Emit_Md_MakeSz_VarVar() local
210 assert(zeroReg == signReg + 1); in Emit_Md_MakeSz_VarVar()
213 m_assembler.Fcmeqz_4s(zeroReg, src1Reg); in Emit_Md_MakeSz_VarVar()
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| /dports/lang/polyml/polyml-5.8.2/mlsource/MLCompiler/CodeTree/X86Code/ |
| H A D | X86ICodeToX86Code.ML | 1809 …val zeroReg = ArithToGenReg { opc=XOR, output=destReg, source=RegisterArg destReg, opSize=OpSize32…
1817 then SOME(instr :: zeroReg :: tl)
1821 then SOME(instr :: zeroReg :: tl)
1825 then SOME(instr :: zeroReg :: tl)
1829 then SOME(instr :: zeroReg :: tl)
1831 … | addXOR ((instr as XMMArith _) :: tl) = SOME(instr :: zeroReg :: tl)
1834 then SOME(instr :: zeroReg :: tl)
1839 then SOME(instr :: zeroReg :: tl)
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| /dports/lang/v8/v8-9.6.180.12/src/compiler/backend/mips64/ |
| H A D | code-generator-mips64.cc | 3639 Simd128Register zeroReg = i.TempSimd128Register(0); in AssembleArchInstruction() local
3640 __ xor_v(zeroReg, zeroReg, zeroReg); in AssembleArchInstruction()
3642 __ vshf_b(dst, zeroReg, tbl); in AssembleArchInstruction()
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| /dports/www/chromium-legacy/chromium-88.0.4324.182/v8/src/compiler/backend/mips64/ |
| H A D | code-generator-mips64.cc | 3559 Simd128Register zeroReg = i.TempSimd128Register(0); in AssembleArchInstruction() local
3560 __ xor_v(zeroReg, zeroReg, zeroReg); in AssembleArchInstruction()
3562 __ vshf_b(dst, zeroReg, tbl); in AssembleArchInstruction()
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| /dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/v8/src/compiler/backend/mips64/ |
| H A D | code-generator-mips64.cc | 3198 Simd128Register zeroReg = i.TempSimd128Register(0); in AssembleArchInstruction() local
3199 __ fill_d(zeroReg, zero_reg); in AssembleArchInstruction()
3201 __ vshf_b(dst, tbl, zeroReg); in AssembleArchInstruction()
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| /dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/v8/src/compiler/backend/mips/ |
| H A D | code-generator-mips.cc | 3145 Simd128Register zeroReg = i.TempSimd128Register(0); in AssembleArchInstruction() local
3146 __ fill_w(zeroReg, zero_reg); in AssembleArchInstruction()
3148 __ vshf_b(dst, tbl, zeroReg); in AssembleArchInstruction()
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| /dports/lang/v8/v8-9.6.180.12/src/compiler/backend/mips/ |
| H A D | code-generator-mips.cc | 3469 Simd128Register zeroReg = i.TempSimd128Register(0); in AssembleArchInstruction() local
3470 __ fill_w(zeroReg, zero_reg); in AssembleArchInstruction()
3472 __ vshf_b(dst, tbl, zeroReg); in AssembleArchInstruction()
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| /dports/www/chromium-legacy/chromium-88.0.4324.182/v8/src/compiler/backend/mips/ |
| H A D | code-generator-mips.cc | 3328 Simd128Register zeroReg = i.TempSimd128Register(0); in AssembleArchInstruction() local
3329 __ fill_w(zeroReg, zero_reg); in AssembleArchInstruction()
3331 __ vshf_b(dst, tbl, zeroReg); in AssembleArchInstruction()
|