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Searched refs:ADDR_SURF_BANK_WIDTH_1 (Results 1 – 25 of 28) sorted by relevance

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/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v8_0.c2359 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2363 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2367 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2371 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2539 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2543 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2547 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2551 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2555 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2559 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
[all …]
/dragonfly/sys/dev/drm/radeon/
H A Dsi.c2511 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2520 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2529 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2538 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2547 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2556 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2565 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2574 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2583 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2592 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
[all …]
H A Dcik.c2464 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2468 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2472 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2476 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2480 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2484 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2488 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2492 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2496 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2607 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
[all …]
H A Dsid.h1207 # define ADDR_SURF_BANK_WIDTH_1 0 macro
H A Dcikd.h1261 # define ADDR_SURF_BANK_WIDTH_1 0 macro
H A Devergreend.h2218 # define ADDR_SURF_BANK_WIDTH_1 0 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/
H A Dsmu_8_0_enum.h958 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
H A Dsmu_7_1_0_enum.h1117 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
H A Dsmu_7_1_1_enum.h1118 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
H A Dsmu_7_1_2_enum.h1136 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
H A Dsmu_7_1_3_enum.h1172 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
/dragonfly/sys/dev/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_enum.h958 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
H A Dbif_5_0_enum.h1088 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
/dragonfly/sys/dev/drm/amd/include/asic_reg/gmc/
H A Dgmc_8_2_enum.h958 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
H A Dgmc_8_1_enum.h1088 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_enum.h971 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
H A Duvd_5_0_enum.h1101 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_enum.h1043 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
H A Ddce_10_0_enum.h1663 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
H A Ddce_11_0_enum.h5530 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
H A Ddce_11_2_enum.h6168 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
/dragonfly/sys/dev/drm/amd/include/asic_reg/oss/
H A Doss_2_4_enum.h1253 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
H A Doss_3_0_1_enum.h1354 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
H A Doss_3_0_enum.h1387 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_enum.h6200 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator

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