/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | gfx_v8_0.c | 2359 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init() 2363 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init() 2367 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init() 2371 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init() 2539 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init() 2543 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init() 2547 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init() 2551 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init() 2555 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init() 2559 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init() [all …]
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/dragonfly/sys/dev/drm/radeon/ |
H A D | si.c | 2511 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init() 2520 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init() 2529 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init() 2538 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init() 2547 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init() 2556 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init() 2565 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init() 2574 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init() 2583 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init() 2592 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init() [all …]
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H A D | cik.c | 2464 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init() 2468 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init() 2472 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init() 2476 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init() 2480 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init() 2484 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init() 2488 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init() 2492 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init() 2496 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init() 2607 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init() [all …]
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H A D | sid.h | 1207 # define ADDR_SURF_BANK_WIDTH_1 0 macro
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H A D | cikd.h | 1261 # define ADDR_SURF_BANK_WIDTH_1 0 macro
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H A D | evergreend.h | 2218 # define ADDR_SURF_BANK_WIDTH_1 0 macro
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/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/ |
H A D | smu_8_0_enum.h | 958 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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H A D | smu_7_1_0_enum.h | 1117 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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H A D | smu_7_1_1_enum.h | 1118 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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H A D | smu_7_1_2_enum.h | 1136 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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H A D | smu_7_1_3_enum.h | 1172 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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/dragonfly/sys/dev/drm/amd/include/asic_reg/bif/ |
H A D | bif_5_1_enum.h | 958 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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H A D | bif_5_0_enum.h | 1088 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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/dragonfly/sys/dev/drm/amd/include/asic_reg/gmc/ |
H A D | gmc_8_2_enum.h | 958 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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H A D | gmc_8_1_enum.h | 1088 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/ |
H A D | uvd_6_0_enum.h | 971 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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H A D | uvd_5_0_enum.h | 1101 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/ |
H A D | dce_8_0_enum.h | 1043 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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H A D | dce_10_0_enum.h | 1663 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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H A D | dce_11_0_enum.h | 5530 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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H A D | dce_11_2_enum.h | 6168 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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/dragonfly/sys/dev/drm/amd/include/asic_reg/oss/ |
H A D | oss_2_4_enum.h | 1253 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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H A D | oss_3_0_1_enum.h | 1354 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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H A D | oss_3_0_enum.h | 1387 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/ |
H A D | gfx_7_2_enum.h | 6200 ADDR_SURF_BANK_WIDTH_1 = 0x0, enumerator
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