| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | gfx_v8_0.c | 2264 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2274 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2436 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2450 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2625 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2639 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2815 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2829 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
3017 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
3031 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
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| H A D | dce_v10_0.c | 1971 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
1973 ARRAY_1D_TILED_THIN1); in dce_v10_0_crtc_do_set_base()
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| H A D | dce_v11_0.c | 2013 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2015 ARRAY_1D_TILED_THIN1); in dce_v11_0_crtc_do_set_base()
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| /dragonfly/sys/dev/drm/radeon/ |
| H A D | cik.c | 2405 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2418 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2433 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2548 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2561 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2692 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2705 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2772 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2785 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2916 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
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| H A D | evergreen_cs.c | 96 return ARRAY_1D_TILED_THIN1; in evergreen_cs_get_aray_mode()
307 case ARRAY_1D_TILED_THIN1: in evergreen_surface_check()
328 case ARRAY_1D_TILED_THIN1: in evergreen_surface_value_conv_check()
883 surf.mode = ARRAY_1D_TILED_THIN1; in evergreen_cs_track_validate_texture()
890 case ARRAY_1D_TILED_THIN1: in evergreen_cs_track_validate_texture()
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| H A D | si.c | 2542 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init()
2587 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init()
2623 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init()
2757 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init()
2802 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init()
2838 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init()
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| H A D | sid.h | 1183 # define ARRAY_1D_TILED_THIN1 2 macro
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| H A D | cikd.h | 1221 # define ARRAY_1D_TILED_THIN1 2 macro
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| H A D | evergreend.h | 2184 # define ARRAY_1D_TILED_THIN1 2 macro
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/smu/ |
| H A D | smu_8_0_enum.h | 526 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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| H A D | smu_7_1_0_enum.h | 79 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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| H A D | smu_7_1_1_enum.h | 86 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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| H A D | smu_7_1_2_enum.h | 86 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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| H A D | smu_7_1_3_enum.h | 83 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/bif/ |
| H A D | bif_5_1_enum.h | 526 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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| H A D | bif_5_0_enum.h | 36 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/gmc/ |
| H A D | gmc_8_2_enum.h | 526 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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| H A D | gmc_8_1_enum.h | 36 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_6_0_enum.h | 539 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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| H A D | uvd_5_0_enum.h | 49 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/dce/ |
| H A D | dce_8_0_enum.h | 36 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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| H A D | dce_10_0_enum.h | 611 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_enum.h | 221 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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| H A D | oss_3_0_1_enum.h | 922 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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| H A D | oss_3_0_enum.h | 335 ARRAY_1D_TILED_THIN1 = 0x2, enumerator
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