| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | gfx_v8_0.c | 2244 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2248 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2252 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2256 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2260 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2416 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2420 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2424 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2428 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2432 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
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| H A D | dce_v10_0.c | 1951 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
1962 ARRAY_2D_TILED_THIN1); in dce_v10_0_crtc_do_set_base()
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| H A D | dce_v11_0.c | 1993 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2004 ARRAY_2D_TILED_THIN1); in dce_v11_0_crtc_do_set_base()
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| /dragonfly/sys/dev/drm/radeon/ |
| H A D | si.c | 2506 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2515 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2524 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2533 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2551 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2560 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2569 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2721 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2730 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2739 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
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| H A D | cik.c | 2385 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2389 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2393 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2397 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2401 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2528 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2532 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2536 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2540 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2544 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
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| H A D | evergreen_cs.c | 94 return ARRAY_2D_TILED_THIN1; in evergreen_cs_get_aray_mode()
309 case ARRAY_2D_TILED_THIN1: in evergreen_surface_check()
324 case ARRAY_2D_TILED_THIN1: in evergreen_surface_value_conv_check()
881 case ARRAY_2D_TILED_THIN1: in evergreen_cs_track_validate_texture()
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| H A D | sid.h | 1184 # define ARRAY_2D_TILED_THIN1 4 macro
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| H A D | cikd.h | 1222 # define ARRAY_2D_TILED_THIN1 4 macro
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| H A D | evergreend.h | 2185 # define ARRAY_2D_TILED_THIN1 4 macro
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/smu/ |
| H A D | smu_8_0_enum.h | 528 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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| H A D | smu_7_1_0_enum.h | 81 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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| H A D | smu_7_1_1_enum.h | 88 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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| H A D | smu_7_1_2_enum.h | 88 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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| H A D | smu_7_1_3_enum.h | 85 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/bif/ |
| H A D | bif_5_1_enum.h | 528 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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| H A D | bif_5_0_enum.h | 38 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/gmc/ |
| H A D | gmc_8_2_enum.h | 528 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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| H A D | gmc_8_1_enum.h | 38 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_6_0_enum.h | 541 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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| H A D | uvd_5_0_enum.h | 51 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/dce/ |
| H A D | dce_8_0_enum.h | 38 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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| H A D | dce_10_0_enum.h | 613 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_enum.h | 223 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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| H A D | oss_3_0_1_enum.h | 924 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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| H A D | oss_3_0_enum.h | 337 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
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