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Searched refs:AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h12146 #define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 macro
H A Ddce_10_0_sh_mask.h13404 #define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 macro
H A Ddce_11_0_sh_mask.h13410 #define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 macro
H A Ddce_11_2_sh_mask.h14026 #define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 macro
H A Ddce_12_0_sh_mask.h64410 #define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h47188 #define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT … macro