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Searched refs:BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__SHIFT (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_sh_mask.h4071 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__SHIFT … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_sh_mask.h22906 #define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__SHIFT … macro