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Searched refs:BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_sh_mask.h2414 #define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_sh_mask.h640 #define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 macro
H A Dbif_5_1_sh_mask.h610 #define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_sh_mask.h117923 #define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT … macro
H A Dnbio_6_1_sh_mask.h17673 #define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT … macro