/dragonfly/sys/dev/disk/amd/ |
H A D | amd.h | 141 #define MORE2_DRV BIT(0) 145 #define NO_SEEK BIT(4) 386 #define SCSI_PHASE_MASK (BIT(2)+BIT(1)+BIT(0)) 406 #define INTRN_STATE_MASK (BIT(2)+BIT(1)+BIT(0)) 413 #define CLK_FREQ_35MHZ (BIT(2)+BIT(1)+BIT(0)) 414 #define CLK_FREQ_30MHZ (BIT(2)+BIT(1)) 415 #define CLK_FREQ_25MHZ (BIT(2)+BIT(0)) 417 #define CLK_FREQ_15MHZ (BIT(1)+BIT(0)) 427 #define SCSI_ID_ON_BUS (BIT(2)+BIT(1)+BIT(0)) 453 #define EATER_0NS (BIT(7)+BIT(6)) [all …]
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/dragonfly/contrib/wpa_supplicant/src/common/ |
H A D | ieee802_11_defs.h | 32 #define WLAN_GET_SEQ_FRAG(seq) ((seq) & (BIT(3) | BIT(2) | BIT(1) | BIT(0))) 34 (((seq) & (~(BIT(3) | BIT(2) | BIT(1) | BIT(0)))) >> 4) 1549 #define OCE_RELEASE_MASK (BIT(0) | BIT(1) | BIT(2)) 2035 #define MB_CTRL_ROLE_MASK (BIT(0) | BIT(1) | BIT(2)) 2172 BIT(6) | BIT(7) | \ 2173 BIT(8) | BIT(9) | \ 2175 BIT(12) | BIT(13))) 2202 #define HE_MU_AC_PARAM_AIFSN ((u8) (BIT(0) | BIT(1) | BIT(2) | BIT(3))) 2209 #define HE_MU_AC_PARAM_ECWMIN ((u8) (BIT(0) | BIT(1) | BIT(2) | BIT(3))) 2210 #define HE_MU_AC_PARAM_ECWMAX ((u8) (BIT(4) | BIT(5) | BIT(6) | BIT(7))) [all …]
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H A D | defs.h | 21 #define WPA_CIPHER_NONE BIT(0) 22 #define WPA_CIPHER_WEP40 BIT(1) 24 #define WPA_CIPHER_TKIP BIT(3) 25 #define WPA_CIPHER_CCMP BIT(4) 27 #define WPA_CIPHER_GCMP BIT(6) 28 #define WPA_CIPHER_SMS4 BIT(7) 392 BAND_2_4_GHZ = BIT(0), 393 BAND_5_GHZ = BIT(1), 394 BAND_60_GHZ = BIT(2), 407 #define OCE_STA BIT(0) [all …]
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H A D | wpa_ctrl.h | 381 #define WPA_BSS_MASK_ID BIT(0) 382 #define WPA_BSS_MASK_BSSID BIT(1) 383 #define WPA_BSS_MASK_FREQ BIT(2) 386 #define WPA_BSS_MASK_QUAL BIT(5) 387 #define WPA_BSS_MASK_NOISE BIT(6) 388 #define WPA_BSS_MASK_LEVEL BIT(7) 389 #define WPA_BSS_MASK_TSF BIT(8) 390 #define WPA_BSS_MASK_AGE BIT(9) 391 #define WPA_BSS_MASK_IE BIT(10) 400 #define WPA_BSS_MASK_SNR BIT(19) [all …]
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H A D | wpa_common.h | 144 #define WPA_CAPABILITY_MFPR BIT(6) 145 #define WPA_CAPABILITY_MFPC BIT(7) 150 #define WPA_CAPABILITY_PBAC BIT(12) 152 #define WPA_CAPABILITY_OCVC BIT(14) 164 #define WPA_KEY_INFO_TYPE_MASK ((u16) (BIT(0) | BIT(1) | BIT(2))) 171 #define WPA_KEY_INFO_KEY_INDEX_MASK (BIT(4) | BIT(5)) 175 #define WPA_KEY_INFO_ACK BIT(7) 176 #define WPA_KEY_INFO_MIC BIT(8) 177 #define WPA_KEY_INFO_SECURE BIT(9) 178 #define WPA_KEY_INFO_ERROR BIT(10) [all …]
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/dragonfly/contrib/wpa_supplicant/src/crypto/ |
H A D | tls.h | 100 #define TLS_CONN_REQUEST_OCSP BIT(3) 101 #define TLS_CONN_REQUIRE_OCSP BIT(4) 104 #define TLS_CONN_EAP_FAST BIT(7) 106 #define TLS_CONN_EXT_CERT_CHECK BIT(9) 108 #define TLS_CONN_SUITEB BIT(11) 114 #define TLS_CONN_TEAP_ANON_DH BIT(17) 633 #define TLS_DHE_PRIME_511B BIT(3) 634 #define TLS_DHE_PRIME_767B BIT(4) 635 #define TLS_DHE_PRIME_15 BIT(5) 636 #define TLS_DHE_PRIME_58B BIT(6) [all …]
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/dragonfly/contrib/wpa_supplicant/src/ap/ |
H A D | sta_info.h | 19 #define WLAN_STA_AUTH BIT(0) 20 #define WLAN_STA_ASSOC BIT(1) 25 #define WLAN_STA_WMM BIT(9) 26 #define WLAN_STA_MFP BIT(10) 27 #define WLAN_STA_HT BIT(11) 28 #define WLAN_STA_WPS BIT(12) 30 #define WLAN_STA_WDS BIT(14) 32 #define WLAN_STA_WPS2 BIT(16) 33 #define WLAN_STA_GAS BIT(17) 34 #define WLAN_STA_VHT BIT(18) [all …]
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/dragonfly/contrib/wpa_supplicant/wpa_supplicant/ |
H A D | config.h | 358 #define CFG_CHANGED_DEVICE_NAME BIT(0) 359 #define CFG_CHANGED_CONFIG_METHODS BIT(1) 360 #define CFG_CHANGED_DEVICE_TYPE BIT(2) 361 #define CFG_CHANGED_OS_VERSION BIT(3) 362 #define CFG_CHANGED_UUID BIT(4) 363 #define CFG_CHANGED_COUNTRY BIT(5) 364 #define CFG_CHANGED_SEC_DEVICE_TYPE BIT(6) 366 #define CFG_CHANGED_WPS_STRING BIT(8) 367 #define CFG_CHANGED_P2P_INTRA_BSS BIT(9) 371 #define CFG_CHANGED_P2P_PREF_CHAN BIT(13) [all …]
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/dragonfly/sys/dev/virtual/amazon/ena/ena-com/ena_defs/ |
H A D | ena_eth_io_defs.h | 313 #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24) 315 #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26) 317 #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27) 319 #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28) 322 #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4) 324 #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7) 371 #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0) 374 #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0) 376 #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2) 378 #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3) [all …]
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H A D | ena_admin_defs.h | 714 ENA_ADMIN_RSS_L2_DA = BIT(0), 717 ENA_ADMIN_RSS_L2_SA = BIT(1), 720 ENA_ADMIN_RSS_L3_DA = BIT(2), 723 ENA_ADMIN_RSS_L3_SA = BIT(3), 726 ENA_ADMIN_RSS_L4_DP = BIT(4), 729 ENA_ADMIN_RSS_L4_SP = BIT(5), 1006 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 1008 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 1018 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 1039 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) [all …]
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/dragonfly/sys/dev/virtual/amazon/ena/ena-com/ |
H A D | ena_eth_io_defs.h | 314 #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24) 316 #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26) 318 #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27) 320 #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28) 323 #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4) 325 #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7) 372 #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0) 375 #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0) 377 #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2) 379 #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3) [all …]
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H A D | ena_admin_defs.h | 644 ENA_ADMIN_RSS_L2_DA = BIT(0), 647 ENA_ADMIN_RSS_L2_SA = BIT(1), 650 ENA_ADMIN_RSS_L3_DA = BIT(2), 653 ENA_ADMIN_RSS_L3_SA = BIT(3), 656 ENA_ADMIN_RSS_L4_DP = BIT(4), 659 ENA_ADMIN_RSS_L4_SP = BIT(5), 934 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 936 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 946 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 967 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) [all …]
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/dragonfly/sys/dev/drm/include/drm/ |
H A D | drm_mipi_dsi.h | 21 #define MIPI_DSI_MSG_REQ_ACK BIT(0) 23 #define MIPI_DSI_MSG_USE_LPM BIT(1) 114 #define MIPI_DSI_MODE_VIDEO BIT(0) 116 #define MIPI_DSI_MODE_VIDEO_BURST BIT(1) 122 #define MIPI_DSI_MODE_VIDEO_HSE BIT(4) 124 #define MIPI_DSI_MODE_VIDEO_HFP BIT(5) 126 #define MIPI_DSI_MODE_VIDEO_HBP BIT(6) 128 #define MIPI_DSI_MODE_VIDEO_HSA BIT(7) 130 #define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8) 132 #define MIPI_DSI_MODE_EOT_PACKET BIT(9) [all …]
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H A D | drm_ioctl.h | 89 DRM_AUTH = BIT(0), 101 DRM_MASTER = BIT(1), 112 DRM_ROOT_ONLY = BIT(2), 119 DRM_CONTROL_ALLOW = BIT(3), 127 DRM_UNLOCKED = BIT(4), 137 DRM_RENDER_ALLOW = BIT(5),
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/dragonfly/sbin/iscontrol/ |
H A D | iscontrol.h | 42 #define BIT(n) (1 <<(n)) macro 56 #define SESS_CONNECTED BIT(0) 57 #define SESS_DISCONNECT BIT(1) 58 #define SESS_LOGGEDIN BIT(2) 59 #define SESS_RECONNECT BIT(3) 60 #define SESS_REDIRECT BIT(4) 62 #define SESS_NEGODONE BIT(10) // XXX: kludge 64 #define SESS_FULLFEATURE BIT(29) 65 #define SESS_INITIALLOGIN1 BIT(30) 66 #define SESS_INITIALLOGIN BIT(31)
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/dragonfly/sys/dev/crypto/tpm/ |
H A D | tpm_tis.c | 48 #define TPM_ACCESS_LOC_REQ BIT(1) 49 #define TPM_ACCESS_LOC_Seize BIT(3) 50 #define TPM_ACCESS_LOC_ACTIVE BIT(5) 52 #define TPM_ACCESS_VALID BIT(7) 60 #define TPM_INT_STS_CMD_RDY BIT(7) 62 #define TPM_INT_STS_VALID BIT(1) 68 #define TPM_STS_VALID BIT(7) 69 #define TPM_STS_CMD_RDY BIT(6) 70 #define TPM_STS_CMD_START BIT(5) 71 #define TPM_STS_DATA_AVAIL BIT(4) [all …]
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/dragonfly/sys/dev/sound/pcm/ |
H A D | feeder_rate.c | 448 PCM_##BIT##_BPS); \ 458 sx += PCM_##BIT##_BPS; \ 459 sy += PCM_##BIT##_BPS; \ 485 #define Z_CLAMP(v, BIT) \ argument 486 (((v) > PCM_S##BIT##_MAX) ? PCM_S##BIT##_MAX : \ 487 (((v) < PCM_S##BIT##_MIN) ? PCM_S##BIT##_MIN : (v))) 538 ch -= PCM_##BIT##_BPS; \ 556 Z_CLIP_CHECK(v, BIT); \ 557 _PCM_WRITE_##SIGN##BIT##_##ENDIAN(dst, Z_CLAMP(v, BIT)); \ 595 Z_CLIP_CHECK(v, BIT); \ [all …]
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H A D | feeder_mixer.c | 52 intpcm##BIT##_t z; \ 59 src -= PCM_##BIT##_BPS; \ 60 dst -= PCM_##BIT##_BPS; \ 61 count -= PCM_##BIT##_BPS; \ 62 x = PCM_READ_##SIGN##BIT##_##ENDIAN(src); \ 63 y = PCM_READ_##SIGN##BIT##_##ENDIAN(dst); \ 64 z = INTPCM##BIT##_T(x) + y; \ 65 x = PCM_CLAMP_##SIGN##BIT(z); \ 66 _PCM_WRITE_##SIGN##BIT##_##ENDIAN(dst, x); \ 99 AFMT_##SIGN##BIT##_##ENDIAN, PCM_##BIT##_BPS, \ [all …]
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H A D | feeder_volume.c | 51 #define FEEDVOLUME_DECLARE(SIGN, BIT, ENDIAN) \ argument 56 intpcm##BIT##_t v; \ 60 dst += count * PCM_##BIT##_BPS * channels; \ 64 dst -= PCM_##BIT##_BPS; \ 66 x = PCM_READ_##SIGN##BIT##_##ENDIAN(dst); \ 67 v = FEEDVOLUME_CALC##BIT(x, vol[matrix[i]]); \ 68 x = PCM_CLAMP_##SIGN##BIT(v); \ 69 _PCM_WRITE_##SIGN##BIT##_##ENDIAN(dst, x); \ 103 #define FEEDVOLUME_ENTRY(SIGN, BIT, ENDIAN) \ argument 105 AFMT_##SIGN##BIT##_##ENDIAN, \ [all …]
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/dragonfly/sys/dev/drm/i915/ |
H A D | intel_device_info.c | 125 sseu->slice_mask = BIT(0); in cherryview_sseu_info_init() 128 sseu->subslice_mask |= BIT(0); in cherryview_sseu_info_init() 135 sseu->subslice_mask |= BIT(1); in cherryview_sseu_info_init() 183 if (!(sseu->slice_mask & BIT(s))) in gen9_sseu_info_init() 414 disabled_mask |= BIT(PIPE_A); in intel_device_info_runtime_init() 416 disabled_mask |= BIT(PIPE_B); in intel_device_info_runtime_init() 418 disabled_mask |= BIT(PIPE_C); in intel_device_info_runtime_init() 423 case BIT(PIPE_A): in intel_device_info_runtime_init() 424 case BIT(PIPE_B): in intel_device_info_runtime_init() 425 case BIT(PIPE_A) | BIT(PIPE_B): in intel_device_info_runtime_init() [all …]
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H A D | i915_gem_gtt.h | 157 #define GEN8_PDE_IPS_64K BIT(11) 158 #define GEN8_PDE_PS_2M BIT(7) 641 #define PIN_NONBLOCK BIT(0) 642 #define PIN_MAPPABLE BIT(1) 643 #define PIN_ZONE_4G BIT(2) 644 #define PIN_NONFAULT BIT(3) 645 #define PIN_NOEVICT BIT(4) 650 #define PIN_UPDATE BIT(8) 652 #define PIN_HIGH BIT(9) 653 #define PIN_OFFSET_BIAS BIT(10) [all …]
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/dragonfly/usr.bin/systat/ |
H A D | convtbl.c | 42 #define BIT (8) macro 60 [SC_BIT] = { BIT, 1, "b", "bit" }, 61 [SC_KILOBIT] = { BIT, KILO, "Kb", "kbit" }, 62 [SC_MEGABIT] = { BIT, MEGA, "Mb", "mbit" }, 63 [SC_GIGABIT] = { BIT, GIGA, "Gb", "gbit" }, 64 [SC_TERABIT] = { BIT, TERA, "Tb", "tbit" }, 65 [SC_AUTOBIT] = { BIT, 0, "", "autobit" }, 89 tmp >= 1000 / (disp_bits ? BIT : BYTE) && in get_tbl_ptr()
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/dragonfly/contrib/wpa_supplicant/src/drivers/ |
H A D | driver.h | 63 HOSTAPD_CHAN_WIDTH_10 = BIT(0), 64 HOSTAPD_CHAN_WIDTH_20 = BIT(1), 65 HOSTAPD_CHAN_WIDTH_40P = BIT(2), 66 HOSTAPD_CHAN_WIDTH_40M = BIT(3), 67 HOSTAPD_CHAN_WIDTH_80 = BIT(4), 68 HOSTAPD_CHAN_WIDTH_160 = BIT(5), 1945 #define WPA_STA_WMM BIT(1) 1947 #define WPA_STA_MFP BIT(3) 2094 TDLS_PEER_HT = BIT(0), 2095 TDLS_PEER_VHT = BIT(1), [all …]
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/dragonfly/contrib/file/src/ |
H A D | file.h | 370 #define BIT(A) (1 << (A)) macro 376 #define STRING_TEXTTEST BIT(5) 377 #define STRING_BINTEST BIT(6) 378 #define PSTRING_1_BE BIT(7) 379 #define PSTRING_1_LE BIT(7) 380 #define PSTRING_2_BE BIT(8) 381 #define PSTRING_2_LE BIT(9) 382 #define PSTRING_4_BE BIT(10) 383 #define PSTRING_4_LE BIT(11) 384 #define REGEX_LINE_COUNT BIT(11) [all …]
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/dragonfly/sys/dev/disk/iscsi/initiator/ |
H A D | iscsivar.h | 65 #ifndef BIT 66 #define BIT(n) (1 <<(n)) macro 69 #define ISC_SM_RUN BIT(0) 72 #define ISC_LINK_UP BIT(2) 73 #define ISC_CON_RUN BIT(3) 75 #define ISC_KILL BIT(5) 78 #define ISC_FFPHASE BIT(8) 79 #define ISC_FFPWAIT BIT(9) 83 #define ISC_FROZEN BIT(12) 86 #define ISC_HOLD BIT(14) [all …]
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