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Searched refs:BIT_11 (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/netif/msk/
H A Dif_mskreg.h178 #define BIT_11 (1 << 11) macro
295 #define PCI_PATCH_DIR_3 BIT_11
392 #define PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */
407 #define PEX_LS_LINK_TRAIN BIT_11 /* Link Training */
1002 #define GLB_GPIO_TEST_SEL_BASE BIT_11
1224 #define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11
1345 #define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */
1499 #define PHY_M_LEDC_F_INT BIT_11 /* Force Interrupt */
1805 #define GM_GPSR_PAUSE BIT_11 /* Pause State */
1819 #define GM_GPCR_RX_ENA BIT_11 /* Enable Receive */
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/dragonfly/sys/dev/netif/re/
H A Dre.c14771 PhyRegValue |= BIT_11; in re_set_phy_mcu_8168evl_1()
26640 Data &= ~BIT_11; in re_hw_phy_config()
26644 Data &= ~BIT_11; in re_hw_phy_config()
26742 Data &= ~BIT_11; in re_hw_phy_config()
26746 Data &= ~BIT_11; in re_hw_phy_config()
27436 Data &= ~BIT_11; in re_hw_phy_config()
27440 Data &= ~BIT_11; in re_hw_phy_config()
27507 Data &= ~BIT_11; in re_hw_phy_config()
27511 Data &= ~BIT_11; in re_hw_phy_config()
27619 Data &= ~BIT_11; in re_hw_phy_config()
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H A Dre.h1006 BIT_11 = (1 << 11), enumerator