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Searched refs:CGC_CLK_GATE_DLY_TIMER (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dvce_v2_0.c136 tmp |= (CGC_CLK_GATE_DLY_TIMER(0) | CGC_CLK_GATER_OFF_DLY_TIMER(4)); in vce_v2_0_init_cg()
H A Dcikd.h2121 # define CGC_CLK_GATE_DLY_TIMER(x) ((x) << 0) macro