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Searched refs:CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h9342 #define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 macro
H A Dgfx_8_0_sh_mask.h11066 #define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 macro
H A Dgfx_8_1_sh_mask.h11464 #define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h23815 #define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT … macro
H A Dgc_9_1_sh_mask.h25231 #define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h25362 #define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT … macro