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Searched refs:CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h9672 #define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 macro
H A Dgfx_8_0_sh_mask.h11396 #define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 macro
H A Dgfx_8_1_sh_mask.h11794 #define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h24173 #define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT … macro
H A Dgc_9_1_sh_mask.h25589 #define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h25720 #define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT … macro