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Searched refs:CGTS_SM_CTRL_REG__SM_MODE_MASK (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h1002 #define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000e0000L macro
H A Dgfx_7_2_sh_mask.h9319 #define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000 macro
H A Dgfx_8_0_sh_mask.h11043 #define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000 macro
H A Dgfx_8_1_sh_mask.h11441 #define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v8_0.c5927 data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK); in gfx_v8_0_update_medium_grain_clock_gating()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h23794 #define CGTS_SM_CTRL_REG__SM_MODE_MASK … macro
H A Dgc_9_1_sh_mask.h25210 #define CGTS_SM_CTRL_REG__SM_MODE_MASK … macro
H A Dgc_9_2_1_sh_mask.h25341 #define CGTS_SM_CTRL_REG__SM_MODE_MASK … macro