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Searched refs:CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dcik.c1361 tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | in cik_set_vce_clocks()
H A Dvi.c808 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK; in vi_set_vce_clocks()
/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_sh_mask.h57 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 macro
H A Dsmu_7_1_1_sh_mask.h57 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 macro
H A Dsmu_7_0_1_sh_mask.h57 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 macro
H A Dsmu_7_1_0_sh_mask.h57 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 macro
H A Dsmu_7_1_2_sh_mask.h57 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 macro
H A Dsmu_7_1_3_sh_mask.h67 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 macro