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Searched refs:CG_FFCT_0 (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dsumod.h215 #define CG_FFCT_0 0x694 macro
H A Drv770d.h227 #define CG_FFCT_0 0x694 macro
H A Dsumo_dpm.c439 WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK); in sumo_program_tp()
440 WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK); in sumo_program_tp()
H A Dsid.h272 #define CG_FFCT_0 0x7c0 macro
H A Dr600_dpm.c355 WREG32(CG_FFCT_0 + (index * 4), UTC_0(u_t) | DTC_0(d_t)); in r600_set_tc()
H A Dr600d.h1429 #define CG_FFCT_0 0x750 macro
H A Drv770_dpm.c855 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); in rv770_program_tp()
H A Dsi_dpm.c3773 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); in si_program_tp()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsi_dpm.c4239 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); in si_program_tp()