Home
last modified time | relevance | path

Searched refs:CM0_PIPELINED_RENDER_FLUSH_DISABLE (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_pm.c8285 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); in ilk_init_clock_gating()
8911 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); in g4x_init_clock_gating()
H A Di915_reg.h2679 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) macro