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Searched refs:CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h20976 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT … macro
H A Dgc_9_1_sh_mask.h22412 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h22351 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT … macro