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Searched refs:CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h2246 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa macro
H A Dgfx_8_0_sh_mask.h2792 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa macro
H A Dgfx_8_1_sh_mask.h3314 #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa macro