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Searched refs:CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h2035 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800 macro
H A Dgfx_8_0_sh_mask.h2567 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800 macro
H A Dgfx_8_1_sh_mask.h3089 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h550 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK … macro
H A Dgc_9_1_sh_mask.h548 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK … macro
H A Dgc_9_2_1_sh_mask.h537 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK … macro