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Searched refs:CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h4123 #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000 macro
H A Dgfx_8_1_sh_mask.h4645 #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12981 #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK … macro
H A Dgc_9_1_sh_mask.h14410 #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK … macro
H A Dgc_9_2_1_sh_mask.h14275 #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK … macro