Searched refs:CP_INT_CNTL_RING0 (Results 1 – 6 of 6) sorted by relevance
/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | gfx_v9_0.c | 1850 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt() 1851 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt() 1852 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt() 1853 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt() 4353 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_gfx_eop_interrupt_state() 4423 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_reg_fault_state() 4442 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_inst_fault_state()
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H A D | gfx_v8_0.c | 3982 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt() 3983 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt() 3984 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt() 3985 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt() 6751 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, in gfx_v8_0_set_gfx_eop_interrupt_state() 6811 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE, in gfx_v8_0_set_priv_reg_fault_state() 6822 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE, in gfx_v8_0_set_priv_inst_fault_state() 6888 WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag); in gfx_v8_0_set_cp_ecc_int_state()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | si.c | 5134 u32 tmp = RREG32(CP_INT_CNTL_RING0); in si_enable_gui_idle_interrupt() 5142 WREG32(CP_INT_CNTL_RING0, tmp); in si_enable_gui_idle_interrupt() 5939 tmp = RREG32(CP_INT_CNTL_RING0) & in si_disable_interrupt_state() 5941 WREG32(CP_INT_CNTL_RING0, tmp); in si_disable_interrupt_state() 6057 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set() 6089 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
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H A D | sid.h | 1276 #define CP_INT_CNTL_RING0 0xC1A8 macro
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H A D | cik.c | 5796 u32 tmp = RREG32(CP_INT_CNTL_RING0); in cik_enable_gui_idle_interrupt() 5802 WREG32(CP_INT_CNTL_RING0, tmp); in cik_enable_gui_idle_interrupt() 6907 tmp = RREG32(CP_INT_CNTL_RING0) & in cik_disable_interrupt_state() 6909 WREG32(CP_INT_CNTL_RING0, tmp); in cik_disable_interrupt_state() 7084 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set() 7203 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
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H A D | cikd.h | 1331 #define CP_INT_CNTL_RING0 0xC1A8 macro
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