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Searched refs:CP_ME1_PIPE2_INT_CNTL (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dcikd.h1360 #define CP_ME1_PIPE2_INT_CNTL 0xC21C macro
H A Dcik.c6918 WREG32(CP_ME1_PIPE2_INT_CNTL, 0); in cik_disable_interrupt_state()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v8_0.c6896 WREG32_FIELD(CP_ME1_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, in gfx_v8_0_set_cp_ecc_int_state()