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Searched refs:CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h1827 #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20 macro
H A Dgfx_8_1_sh_mask.h2351 #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11850 #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK … macro
H A Dgc_9_1_sh_mask.h13405 #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK … macro