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Searched refs:CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11875 #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT macro
H A Dgc_9_1_sh_mask.h13430 #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT macro