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Searched refs:CP_MEC_CNTL (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Dsmu8_smumgr.c194 tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); in smu8_load_mec_firmware()
195 tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); in smu8_load_mec_firmware()
/dragonfly/sys/dev/drm/radeon/
H A Dcikd.h1094 #define CP_MEC_CNTL 0x8234 macro
1098 #define CP_MEC_CNTL 0x8234 macro
H A Dcik.c4260 WREG32(CP_MEC_CNTL, 0); in cik_cp_compute_enable()
4271 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT)); in cik_cp_compute_enable()
4985 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_soft_reset()
5189 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_pci_config_reset()