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Searched refs:CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h1859 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1 macro
H A Dgfx_8_1_sh_mask.h2381 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11070 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK … macro
H A Dgc_9_1_sh_mask.h12676 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK … macro
H A Dgc_9_2_1_sh_mask.h12474 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK … macro