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Searched refs:CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2702 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003fL macro
H A Dgfx_7_2_sh_mask.h3147 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f macro
H A Dgfx_8_0_sh_mask.h3761 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f macro
H A Dgfx_8_1_sh_mask.h4283 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1150 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK … macro
H A Dgc_9_1_sh_mask.h1148 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK … macro
H A Dgc_9_2_1_sh_mask.h1115 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK … macro