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Searched refs:CP_RB0_CNTL__CACHE_POLICY_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2712 #define CP_RB0_CNTL__CACHE_POLICY_MASK 0x03000000L macro
H A Dgfx_7_2_sh_mask.h1051 #define CP_RB0_CNTL__CACHE_POLICY_MASK 0x3000000 macro
H A Dgfx_8_0_sh_mask.h1369 #define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000 macro
H A Dgfx_8_1_sh_mask.h1893 #define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h10578 #define CP_RB0_CNTL__CACHE_POLICY_MASK … macro
H A Dgc_9_1_sh_mask.h12184 #define CP_RB0_CNTL__CACHE_POLICY_MASK … macro
H A Dgc_9_2_1_sh_mask.h11989 #define CP_RB0_CNTL__CACHE_POLICY_MASK … macro