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Searched refs:CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h3179 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d macro
H A Dgfx_7_2_sh_mask.h2588 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d macro
H A Dgfx_8_0_sh_mask.h3152 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d macro
H A Dgfx_8_1_sh_mask.h3674 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h19280 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT … macro
H A Dgc_9_1_sh_mask.h20716 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h20643 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT … macro