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Searched refs:DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h3322 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00100000L macro
H A Dgfx_7_2_sh_mask.h3977 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000 macro
H A Dgfx_8_0_sh_mask.h4703 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000 macro
H A Dgfx_8_1_sh_mask.h5227 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h4982 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK … macro
H A Dgc_9_1_sh_mask.h4555 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK … macro
H A Dgc_9_2_1_sh_mask.h4384 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK … macro