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Searched refs:DCIO_GENLK_VSYNC_GSL_MASK_TIMING (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_enum.h283 DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x1, enumerator
H A Ddce_11_0_enum.h1052 DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x1, enumerator
H A Ddce_11_2_enum.h1451 DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x1, enumerator
/dragonfly/sys/dev/drm/amd/include/
H A Dvega10_enum.h11974 DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x00000001, enumerator