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Searched refs:DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_enum.h422 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x4, enumerator
H A Ddce_11_0_enum.h1187 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x4, enumerator
H A Ddce_11_2_enum.h1594 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x4, enumerator
/dragonfly/sys/dev/drm/amd/include/
H A Dvega10_enum.h12212 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x00000004, enumerator