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Searched refs:DCIO_GSL_VSYNC_SEL_PIPE0 (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_enum.h297 DCIO_GSL_VSYNC_SEL_PIPE0 = 0x0, enumerator
H A Ddce_11_0_enum.h1066 DCIO_GSL_VSYNC_SEL_PIPE0 = 0x0, enumerator
H A Ddce_11_2_enum.h1465 DCIO_GSL_VSYNC_SEL_PIPE0 = 0x0, enumerator
/dragonfly/sys/dev/drm/amd/include/
H A Dvega10_enum.h12003 DCIO_GSL_VSYNC_SEL_PIPE0 = 0x00000000, enumerator