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Searched refs:DCIO_GSL_VSYNC_SEL_PIPE5 (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_enum.h302 DCIO_GSL_VSYNC_SEL_PIPE5 = 0x5, enumerator
H A Ddce_11_0_enum.h1071 DCIO_GSL_VSYNC_SEL_PIPE5 = 0x5, enumerator
H A Ddce_11_2_enum.h1470 DCIO_GSL_VSYNC_SEL_PIPE5 = 0x5, enumerator
/dragonfly/sys/dev/drm/amd/include/
H A Dvega10_enum.h12008 DCIO_GSL_VSYNC_SEL_PIPE5 = 0x00000005, enumerator