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Searched refs:DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h4125 #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000 macro
H A Ddce_10_0_sh_mask.h4051 #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000 macro
H A Ddce_11_0_sh_mask.h4165 #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000 macro
H A Ddce_11_2_sh_mask.h4609 #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000 macro
H A Ddce_12_0_sh_mask.h10560 #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h41170 #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK … macro