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Searched refs:DC_HPD1_INT_CONTROL (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/irq/dce80/
H A Dirq_service_dce80.c59 DC_HPD1_INT_CONTROL, in hpd_ack()
/dragonfly/sys/dev/drm/radeon/
H A Dr600.c858 tmp = RREG32(DC_HPD1_INT_CONTROL); in r600_hpd_set_polarity()
863 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
3646 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3647 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3798 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3894 WREG32(DC_HPD1_INT_CONTROL, hpd1); in r600_irq_set()
3965 tmp = RREG32(DC_HPD1_INT_CONTROL); in r600_irq_ack()
3967 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_irq_ack()
H A Dcik.c6957 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
6958 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7088 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7242 WREG32(DC_HPD1_INT_CONTROL, hpd1); in cik_irq_set()
7343 tmp = RREG32(DC_HPD1_INT_CONTROL); in cik_irq_ack()
7345 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack()
7373 tmp = RREG32(DC_HPD1_INT_CONTROL); in cik_irq_ack()
7375 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack()
H A Dsid.h880 #define DC_HPD1_INT_CONTROL 0x6020 macro
H A Dcikd.h954 #define DC_HPD1_INT_CONTROL 0x6020 macro
H A Devergreend.h1346 #define DC_HPD1_INT_CONTROL 0x6020 macro
H A Dr600d.h856 #define DC_HPD1_INT_CONTROL 0x7d04 macro
H A Devergreen.c39 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
H A Dsi.c153 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))