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Searched refs:DC_HPD5_INT_CONTROL (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dr600.c890 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_hpd_set_polarity()
895 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_hpd_set_polarity()
3655 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3656 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3803 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3899 WREG32(DC_HPD5_INT_CONTROL, hpd5); in r600_irq_set()
4003 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_irq_ack()
4005 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_irq_ack()
H A Dcik.c6965 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
6966 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7092 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7246 WREG32(DC_HPD5_INT_CONTROL, hpd5); in cik_irq_set()
7363 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7365 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
7393 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7395 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
H A Dsid.h884 #define DC_HPD5_INT_CONTROL 0x6050 macro
H A Dcikd.h958 #define DC_HPD5_INT_CONTROL 0x6050 macro
H A Devergreend.h1350 #define DC_HPD5_INT_CONTROL 0x6050 macro
H A Dr600d.h861 #define DC_HPD5_INT_CONTROL 0x7dc4 macro