Searched refs:DC_ISR (Results 1 – 3 of 3) sorted by relevance
| /dragonfly/sys/dev/netif/dc/ |
| H A D | if_dc.c | 1362 isr = CSR_READ_4(sc, DC_ISR); in dc_setcfg()
2744 r = CSR_READ_4(sc, DC_ISR); in dc_tick()
2815 isr = CSR_READ_4(sc, DC_ISR); in dc_tx_underrun()
2864 status = CSR_READ_4(sc, DC_ISR); in dc_npoll_compat()
2871 CSR_WRITE_4(sc, DC_ISR, status); in dc_npoll_compat()
2942 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) in dc_intr()
2947 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) in dc_intr()
2955 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && in dc_intr()
2958 CSR_WRITE_4(sc, DC_ISR, status); in dc_intr()
3313 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); in dc_init()
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| H A D | if_dcreg.h | 44 #define DC_ISR 0x28 /* interrupt status register */ macro
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| /dragonfly/sys/dev/netif/mii_layer/ |
| H A D | pnphy.c | 265 reg = CSR_READ_4(dc_sc, DC_ISR); in pnphy_status()
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